We develop VLSI circuit technologies for AI/IoT era. Training large-scale language models such as GPT-4 consumes massive power equivalent to several nuclear power plants. Low-power AI processing is essential for better world empowerd by large-scale AI models. We aim to develop (1) a highly energy-efficient domain specific processor by co-optimizing algorithms and VLSI circuits, and (2) 2.5D/3D chip stacking technology to reduce the power consumption required for massive data-movement between processor cores and memories.

To improve processor performance, it is necessary to reduce the communication power between the memory and the processor. However, as the number of memory chips mounted inside the package increases, heat cannot removed from the package, resulting in malfunction caused by high temperature. We study new 2.5D/3D chip stacking technology with newly proposed wireless data communication method that can easily dissipate heat. We are studying (1) a new semiconductor packaging technology based on short-range wireless communication technology and (2) ultra-low power memory-to-processor data communication circuit technology.